1. Field of the Invention
The present invention relates to an AC driving type plasma display driving method and apparatus.
2. Description of the Related Art
In recent years, plasma display panels (PDPs) have received a great deal of attention as a next-generation display device in place of CRTs because the PDPs are self-emission type display devices with good visibility, and can realize a low-profile large-screen display. In particular, an AC driving type PDP that can realize a large screen, is expected as a display device coping with high-quality digital broadcasting, and is demanded to attain higher image quality than the CRT.
FIG. 1 is a circuit diagram showing the whole arrangement of an AC driving type PDP apparatus. In FIG. 1, an AC driving type PDP 1 comprises scanning electrodes Y1 to Yn and common electrodes X parallel to each other on one surface, and address electrodes A1 to Am perpendicular to these electrodes Y1 to Yn and X on the opposing surface. The common electrodes X are laid out close to the scanning electrodes Y1 to Yn in correspondence with them, and have terminals commonly connected.
The common terminal of the common electrodes X is connected to the output terminal of an X driver 2, the scanning electrodes Y1 to Yn are connected to the output terminals of a Y driver 3, and the address electrodes A1 to Am are connected to the output terminals of an address driver 4. The X driver 2, Y driver 3, and address driver 4 are controlled by control signals from a controller 5.
The controller 5 generates the control signals on the basis of external display data D, clock CLK indicating the read timing of the display data D, horizontal sync signal HS, and vertical sync signal VS, and supplies the control signals to the X driver 2, Y driver 3, and address driver 4.
FIG. 2 is a sectional view showing the structure of a cell Cij as one pixel on the i-th row and j-th column. In FIG. 2, a common electrode X and a scanning electrode Yi are formed on a front glass substrate 11. The common electrode X and scanning electrode Yi are covered with a dielectric layer 12 for insulating them from a discharge space 17, and the dielectric layer 12 is covered with a MgO (magnesium oxide) protective film 13.
An address electrode Aj is formed on a rear glass substrate 14 facing the front glass substrate 11, and covered with a phosphor 15. Ribs 16 for preventing color mixing between cells and maintaining a discharge gap are formed at pixel boundaries on the rear glass substrate 14 and address electrode Aj. Ne+Xe Penning gas is sealed in the discharge space 17 between the MgO protective film 13 and phosphor 15.
FIG. 3 is a voltage waveform chart showing an example of an AC driving type PDP driving method. FIG. 3 shows one of the subfields constituting one frame. Each subfield is divided into a reset period comprising a full-surface write period and full-surface erase period, address period, and sustain discharge period.
In the reset period, all scanning electrodes Y1 to Yn change to the ground level (0 V). At the same time, a full-surface write pulse of a voltage Vs+Vw (about 330 V) is applied to the common electrode X. At this time, all address electrodes A1 to Am are at a potential Vaw (about 100 V). As a result, all cells on all display lines discharge to generate wall charges regardless of the preceding display state.
The potentials of the common electrode X and address electrodes A1 to Am change to 0 V, and the voltages of wall charges themselves exceed the discharge start voltage in all cells to start discharging. During this discharge, since the electrodes do not have any potential difference, no wall charge is generated so that space charges self-neutralize to stop discharging. This is so-called self-erase discharge. This self-erase discharge makes all cells in the panel uniform freely from any wall charge. In this reset period, all cells can be made uniform regardless of the ON state of each cell in the preceding subfield. Thus, the next address (write) discharge can be stably performed.
In the address period, address discharges are done line-sequentially in order to turn each cell on/off in accordance with display data. More specifically, a scan pulse of xe2x88x92Vy level (about xe2x88x92150 V) is applied to the scanning electrode Y1 corresponding to the first display line. At the same time, an address pulse of a voltage Va (about 50 V) is selectively applied to a cell that causes sustain discharge among the address electrodes A1 to Am, i.e., the address electrode Aj corresponding to a cell to be turned on.
Consequently, a discharge occurs between the address electrode Aj and scanning electrode Y1 of the cell to be turned on. Using this discharge as a priming effect (firing), the common electrode X of a voltage Vx (about 50 V) and scanning electrode Y1 immediately discharge. Then, a sufficient amount of wall charges for the next sustain discharge are accumulated in the MgO protective film 13 on the common electrode X and scanning electrode Y1 of the selected cell. The same processing is done for the scanning electrodes Y2 to Yn corresponding to the other display lines, and new display data are written in all display lines.
In the sustain discharge period, a sustain pulse of a voltage Vs (about 180 V) is alternately applied to the scanning electrodes Y1 to Yn and common electrode X to perform sustain discharges so as to achieve a video display of one subfield. Note that the length of the sustain discharge period, i.e., the number of sustain pulses determine the video luminance.
In the above driving method, each subfield in one frame has the reset period, and a full-surface write discharge by application of the full-surface write pulse is done in each subfield. For this reason, each subfield emits light in the reset period not originally contributing to the video display, which decreases the video display contrast.
To solve this problem, the present applicant has invented and filed a driving method that realizes high contrast by decreasing the number of full-surface write discharges per frame (Japanese Patent Application Laid-Open No. 313598/1993). According to this driving method, the full-surface write discharge in the reset period is executed in only part of subfields in one frame, and only erase discharges in the reset period are executed in the remaining subfields.
In this high-contrast driving method, an erase discharge is performed in the reset period of the next subfield SFn+1 immediately after the sustain discharge (sustain) period of the n-th subfield SFn, as shown in FIG. 4. In this case, an erase pulse made of a small-width pulse (e.g., a pulse width of 2 xcexcs or less) is applied to the common electrode X to erase wall charges of each electrode only from the cell which was turned on in the preceding subfield SFn.
An allowable range (voltage range from the minimum value to the maximum value will be called a driving voltage margin) is defined for the voltage values of various pulses for realizing driving of normally turning an ON cell on based on display data while keeping an OFF cell off. If the discharge starts unexpectedly early owing to nonuniform pixels and temperature condition changes in the small-width erase discharge during the reset period, a necessary wall charge erase fails. In addition, wall charges opposite in polarity to wall charges before an erase may be generated on the common electrode X and scanning electrode Y. This narrows the driving voltage margin.
To solve this problem, the present applicant has further invented and filed a new driving method (U.S. patent application Ser. No. 115911 filed on Jul. 15, 1998). According to this driving method, after a small-width pulse is applied during the reset period, another erase pulse (Slope Erase Pulse: SEP) which rises with a gradual slope is applied to make an erroneous erase state come close to a more complete erase state.
FIG. 5 shows an example of this driving method. FIG. 5 is a driving waveform chart showing part of the reset period in a given subfield. In an ON cell in which the final sustain discharge was done in a preceding subfield, positive and negative charges are respectively accumulated in the common electrode X and scanning electrode Y. In this state, an erase pulse of the voltage Vs made of a small-width pulse is applied to the common electrode X to erase wall charges of the ON cell, as shown in FIG. 5.
Note that the small-width pulse terminates application of the pulse voltage immediately after a discharge. Most of charge particles generated by the discharge are left in the discharge cell space, attracted by an electrostatic attraction to wall charges of the dielectric layer of the panel, and recombine each other and disappear on the wall surface. Such a strong discharge using a rectangular wave, however, may generate new wall charges opposite in polarity to wall charges before an erase, in the common electrode X and scanning electrode Y, as described above.
To prevent this, after an erase discharge using the small-width pulse is performed, an erase pulse (to be referred to as a positive obtuse wave) which rises to the voltage Vs with a gradual slope and an erase pulse (to be referred to as a negative obtuse wave) which falls to a voltage xe2x88x92Vy with a gradual slope are sequentially applied. Wall charges having an inverted polarity which are left owing to an excessive reaction with the small-width pulse, and wall charges which cannot completely be erased by the erase discharge using the small-width pulse are reacted and erased with the potentials of the positive and negative obtuse waves which gradually change with time.
More specifically, the amount of wall charges accumulated in a cell which was turned on in the preceding subfield is not always the same in all cells, so the discharge start voltage of each cell varies. If such obtuse waves are applied in this state, discharges sequentially occur from cells in which the pulse voltage during the rise of the positive obtuse wave and the fall of the negative obtuse wave reaches the discharge voltage. Each cell substantially receives the optimum voltage (voltage almost equal to the discharge start voltage). This can erase the residual charges.
In this related art, however, the erase discharge is done only for the cell, which was turned on in the preceding subfield among subfields except for a specific subfield in the high-contrast driving method. Under the influence of wall charges accumulated in the ON cell, charges may be accumulated in an OFF cell, which has been kept off, may not be erased, and may be left. FIGS. 6A to 6C are representations for respectively illustrating the states of charges accumulated in the OFF cell.
As shown in FIG. 6A, in an ON cell in which the final sustain discharge was done in the preceding subfield, positive charges are accumulated in its address electrode A and common electrode X, and negative charges are accumulated in its scanning electrode Y. Even in an OFF cell adjacent to the ON cell, weak positive wall charges are accumulated in its address electrode A and scanning electrode Y of the OFF cell, and weak negative wall charges are accumulated in its common electrode X under the influence of the wall charges accumulated in the ON cell.
If an erase discharge using the small-width pulse is executed in this state during the reset period of the next subfield, new wall charges opposite in polarity to the wall charges before being erased may be generated on the common electrode X and scanning electrode Y, as shown in FIG. 6B. If the erase discharge using the obtuse wave as shown in FIG. 5 is executed, wall charges accumulated in the ON cell are erased to be free from any residual charges, as shown in FIG. 6C.
The ON cell accumulates charges enough for satisfactorily starting discharging by the pulse voltage during the rise of the positive obtuse wave and the fall of the negative obtuse wave. By applying these positive and negative obtuse waves, the discharge can occur to erase residual charges. In the OFF cell, however, wall charges accumulated under the influence of the adjacent ON cell are weak. Even if the pulse voltage of the obtuse wave changes to the voltage Vs or xe2x88x92Vy, the OFF cell cannot reach the discharge start voltage, so wall charges cannot be erased and are left.
In this case, if the cell is kept off for several frames, like a still image and the background of a moving picture, the amount of residual charges accumulated in the OFF cell increases gradually. If a sufficient amount of residual charges, which cannot react with respect to the positive and negative obtuse waves, is accumulated in the OFF cell, the OFF cell which should not be turned on is turned on under the influence of residual charges to narrow the driving voltage margin.
FIG. 7 is a representation for illustrating this conventional problem. As shown in FIG. 7, a scan pulse of xe2x88x92Vy level is applied to scanning electrodes Yi and Yi+2 of cells C1 and C3 to be turned on in accordance with display data. At the same time, an address pulse of Va level is selectively applied to an address electrode A corresponding to the cells to be turned on, so as to emit light from the cells.
But, if a sufficient amount of residual charges is accumulated in an OFF cell C2 not to be turned on, an address pulse is applied owing to positive charges on the address electrode A to operate the cell C2 as if a scan pulse is applied owing to negative charges on a scanning electrode Yi+1. This causes a miss discharge in the OFF cell to generate wall charges. A sustain discharge is undesirably done in the OFF cell during the subsequent sustain discharge period to turn on the OFF cell though it should not be turned on.
The present invention has been made to overcome the conventional drawbacks, and aims to improve the driving voltage margin in driving a PDP, and reliably to realize driving of normally turning on an ON cell that should be turned on based on display data while keeping an OFF cell off.
To achieve the above object, in a plasma display driving method according to the present invention, each frame comprises subfields; each of the subfields includes a reset period for performing an erase discharge to make a wall charge distribution in each cell uniform, an address period for generating wall charges in a cell to be turned on in accordance with display data, and a sustain discharge period for discharging the wall charges accumulated in the cell during the address period, to emit light; and the reset period includes first and second erase discharge periods for performing erase discharges for cells having been turned on and not having been turned on, respectively.
The present invention can apply to a so-called high-contrast driving method. In this case, erase discharges done separately in the first and second erase discharge periods are executed in subfields except for a specific subfield.
A plasma display driving apparatus according to the present invention is for driving a plasma display panel in each of the subfields constituting one frame. Each of the subfields includes a reset period for performing an erase discharge to make a wall charge distribution in each cell uniform, an address period for generating wall charges in a cell to be turned on in accordance with display data, and a sustain discharge period for discharging the wall charges accumulated in the cell during the address period, to emit light. The apparatus comprises control means for performing erase discharges for cells having been turned on and not having been turned on, in first and second erase discharge periods in the reset period, respectively.
According to the present invention having the above features, during the reset period after the sustain discharge period, an erase discharge is done in the first erase discharge period for an ON cell turned on in the preceding sustain discharge period, so as to erase wall charges in the ON cell, for example. Even for an OFF cell not turned on in the preceding sustain discharge period, an erase discharge is done in the second erase discharge period on the basis of a pulse voltage having a different waveform from that for the ON cell. As a result, even weak wall charges accumulated in the OFF cell under the influence of the ON cell can be erased.
For example, the erase discharge for the OFF cell is achieved by applying to the first electrode the first erase pulse whose application voltage continuously changes with time in a positive direction, and applying to the second electrode the second erase pulse whose application voltage continuously changes with time in a negative direction. This can widen the potential difference between the first and second electrodes to erase even weak wall charges accumulated in the OFF cell under the influence of the ON cell.
In other words, the present invention performs erase discharges for ON and OFF cells in the first and second erase discharge periods in the reset period, respectively. Weak wall charges that could not completely be erased in the first erase discharge period, i.e., weak wall charges accumulated in the OFF cell under the influence of the ON cell can be erased in the second erase discharge period. This makes it possible to prevent an ON operation of the OFF cell that should not be turned on in the subsequent address period and sustain discharge period, and to improve the driving voltage margin.